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Description
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PLL
(Phase Locked Loop)
generates a number
of clocks required
for TX block operation.
PLL, synchronized to
the external reference
clock of 37.5MHz,
generates 1.5GHz
clock and this clock
is divided into
375MHz, 150MHz,
and 37.5MHz clocks.
The Spread Spectrum
Clock (SSC) is to
adjust the spread
technique not to
allow modulation
above the nominal
frequency. A triangular
frequency modulation
profile is shown
below where is
the nominal frequency
in non-SSC mode,
is the
modulation frequency,
and δ is the modulation
amount.
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For
triangular modulation,
it is required that
the clock frequency
deviation (δ) be
no more than 0.5%
“down spread”
from the corresponding
nominal frequency,
i.e. +0%/-0.5%.
Swallow
counter is used
to realize the SSC
function. When SSC
is off, PLL divides
the source clock
N times, and when
SSC is on, the source
clock is divided
into N or N-1 times
with proper ratio.
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Features
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Items
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Value
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Unit
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| Speed |
1.5
|
GHz
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| Spreading
Ratio (Down
Spreading) |
-0.5
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%
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| Spreading
Interval |
31.25
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KHz
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| Setting
Time |
10~100
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uSec
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| Ref.
Clock |
37.5
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MHz
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| Jitter
w/o SSC |
<220
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pSec
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▷
Recommend Application
-. High-speed
network application
-. Serial
communication devices,
which is required
to calibrate impedance
between TX and RX.
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